Nuvoton NuMicro M23

The NuMicro M2351 was Nuvoton's first TrustZone-M chip and one of the earliest Cortex-M23 parts to ship in volume — sampling in 2018, in production by mid-2019, alongside STM's L5 series. The pitch is the same as L5 and Microchip SAM L11 in the same era: bring ARMv8-M TrustZone down from the M33 high-end into the entry tier, package it with a credible crypto engine, ROM-based secure boot, and tamper-detection logic, and offer the result as a one-chip security platform for IoT endpoints, secure payment dongles, asset trackers, and provisioning-sensitive industrial devices. M2354 followed in 2021 with higher clocks, more flash, and PSA Certified Level 2 silicon certification.

The two parts

Both share the same security architecture; M2354 is the recommended part for new designs, with M2351 kept alive for existing customers.

What Cortex-M23 brings

Cortex-M23 is the entry tier of ARMv8-M — a stripped-down M33 without the FPU, without DSP extensions, with a simpler two-stage pipeline running at roughly 0.98 DMIPS/MHz (compared to 1.5 DMIPS/MHz on M4F and 1.5 DMIPS/MHz on M33). The reason to use M23 instead of M0+ is the Security Extension — the same TrustZone-M technology found on M33, dropped into a lower-cost lower-power core. You get the secure/non-secure partition, the SAU (Security Attribution Unit), the IDAU, secure function entry points (NSC regions), but without the FPU/MVE/coprocessor overhead.

For an IoT endpoint that mostly waits, occasionally measures a sensor, and needs to verify a signed firmware update once a week, the M23 has all the security architecture and none of the FPU cost. It is a deliberate choice for cost-sensitive secure designs.

The M2351 / M2354 security stack

Nuvoton wraps the M23 core with a stack of hardware blocks that together provide a documented PSA Certified Level 2 implementation:

The result is a part that meets PSA Certified Level 2 — independently evaluated by SGS Brightsight (the PSA certification body) and listed on the PSA Certified registry. Level 2 means the silicon has been audited against attacks including side-channel analysis (DPA, SPA), fault injection (clock glitching, voltage glitching, laser fault injection), and software exploitation, and has provided documented countermeasures.

Power consumption

For a battery-powered secure IoT endpoint, the active-mode current matters as much as the security:

M2354's deep-sleep numbers are competitive with STM32L5 (~1.5 µA Stop 2 with RTC) but not class-leading — for sub-µA sleep on a TrustZone part, STM32U5 or Ambiq Apollo4 are still ahead. Where M2354 wins is on price: roughly USD 2.50 in 10k volume against USD 4.50 for STM32L5 and USD 5.20 for STM32U5 at equivalent flash/SRAM.

TrustZone-M model

The ARMv8-M Security Extension partitions all memory and all peripherals between two worlds:

• Secure world (S) — holds the secure boot bootloader, the crypto provisioning code, the firmware update verification routine, the cryptographic keys (in Key Store), and any other code that must never be tampered with.
• Non-secure world (NS) — runs the application: sensor sampling, business logic, network stack, RTOS.

Non-secure code calls into secure code only through documented entry points (__attribute__((cmse_nonsecure_entry)) functions in NSC — Non-Secure Callable — flash regions). The hardware enforces this; a stray jump from NS code into the middle of a secure function triggers a SecureFault.

The SAU (Security Attribution Unit) is the table that tells the CPU which addresses are secure and which are non-secure. It is configured at boot by the secure-world code. Get it wrong — for example, mark a region as NSC that contains data instead of valid entry-point gateways — and the system will fault on legitimate calls.

/* Configure SAU regions on M2354 to partition the address space.
 * Run from secure-world code very early in boot, before NS image is launched. */
 
#include "NuMicro.h"
#include "partition_M2354.h"
 
void sau_init(void)
{
    /* SAU region 0: 0x00100000 - 0x001FFFFF = APROM NS region.
     * The first 0x100000 (1 MB / 2) is secure; second 0x100000 is NS. */
    SAU->RNR  = 0;
    SAU->RBAR = (0x00100000u & SAU_RBAR_BADDR_Msk);
    SAU->RLAR = (0x001FFFE0u & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
 
    /* SAU region 1: NSC veneer table. 0x000FFE00 - 0x000FFFFF.
     * Holds the cmse_nonsecure_entry trampolines that NS code calls. */
    SAU->RNR  = 1;
    SAU->RBAR = (0x000FFE00u & SAU_RBAR_BADDR_Msk);
    SAU->RLAR = (0x000FFFE0u & SAU_RLAR_LADDR_Msk)
              | SAU_RLAR_NSC_Msk | SAU_RLAR_ENABLE_Msk;
 
    /* SAU region 2: 0x20100000 - 0x2017FFFF = SRAM NS region.
     * SRAM bank 0 stays secure; bank 1 is non-secure. */
    SAU->RNR  = 2;
    SAU->RBAR = (0x20100000u & SAU_RBAR_BADDR_Msk);
    SAU->RLAR = (0x2017FFE0u & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
 
    /* SAU region 3: 0x40000000 peripheral region — most peripherals NS,
     * but specific blocks (CRYPTO, KS, FMC, SCU) remain secure-only via
     * the SCU peripheral attribution registers, configured separately. */
    SAU->RNR  = 3;
    SAU->RBAR = (0x40000000u & SAU_RBAR_BADDR_Msk);
    SAU->RLAR = (0x4FFFFFE0u & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
 
    /* Enable SAU. ALLNS = 0 means use the region table; default to S. */
    SAU->CTRL = SAU_CTRL_ENABLE_Msk;
 
    __DSB(); __ISB();
}

The companion partition_M2354.h header — generated by NuTool — defines the SAU regions and the SCU (Security Configuration Unit) peripheral attribution table in a form the compiler can validate. NuTool's GUI lets you click regions onto a memory map and exports the header; it is by far the safest way to author the partition.

TF-M support

Nuvoton maintains a Trusted Firmware-M (TF-M) port for M2351 and M2354 in the upstream TF-M tree (platform/ext/target/nuvoton/). TF-M is the reference PSA implementation maintained by Arm — it provides the Internal Trusted Storage (ITS), Protected Storage (PS), Cryptographic Service, Attestation Service, and Firmware Update Service, all running in secure world and exposed to non-secure applications through PSA APIs. Using TF-M means your application calls psa_crypto_init() and psa_aead_encrypt() instead of vendor-specific crypto APIs, which makes porting between PSA-certified silicon (STM32L5/U5, NuMicro M2354, NXP LPC55, Microchip SAM L11) much easier.

The Nuvoton TF-M port is functional but trails ST's TF-M support by about a release; for production work pin to a specific TF-M tag rather than tracking master.

Anti-tamper hardware

M2354 has six tamper-detect input pins. Each can be configured for:

• Static detection — input level transitions trigger a tamper event.
• Dynamic detection — input must match a pseudorandom pattern generated by an LFSR; an attacker driving the pin to a static level triggers a tamper event.
• Differential detection — paired pins must always be at opposite levels; if shorted, tamper triggers.

When a tamper event fires, the hardware can be configured to: clear the Key Store automatically, log the event with a timestamp from the RTC backup register, hold the CPU in reset, or assert a tamper output pin for an external supervisor. All without CPU involvement — even if the application firmware is compromised, tamper detection still functions.

Where to use M2354

Strong fit: secure payment terminals (POS, mPOS, EMV card readers), IoT endpoints needing PSA Certified Level 2 silicon (regulatory pressure rising in EU under EN 18031), asset trackers with tamper-protected provisioned keys, secure firmware-over-the-air for industrial sensors, smart-lock electronics, electricity meters with privacy-sensitive consumption data. Weak fit: anything needing FPU (M23 has none — move to NuMicro M4 with software-only secure boot, or upgrade to STM32U5 for M33 + TrustZone + FPU).

Cross-references

• NuMicro landing page
• NuMicro M0 entry
• NuMicro M4 mainstream
• Cortex-M23
• STM32 low-power L5 and U5 — direct comparison for TrustZone IoT
• NuMicro M2354 product page (external)
• Nuvoton TF-M port on GitHub (external)
• PSA Certified registry (external — search for Nuvoton)