Glossary

Every term, one page.

Acronyms, register names, ARM-isms — short definitions with links to the full deep-dives. Skim or jump straight to the letter you need.

A

8 terms

AAPCS: Procedure Call Standard for ARM — calling convention defining how parameters, returns, and registers behave across function boundaries.
ADC: Analog-to-Digital Converter. Samples a continuous voltage and produces a digital code (typically 10–16 bits on Cortex-M).
AHB: Advanced High-performance Bus. ARM AMBA bus used to connect CPU, memory, and high-bandwidth peripherals on Cortex-M SoCs.
APB: Advanced Peripheral Bus. Slower-speed companion to AHB; used for register-mapped peripherals.
ARMv6-M / v7-M / v8-M: ARM M-profile ISA versions. v6-M = Cortex-M0/M0+, v7-M = Cortex-M3, v7E-M = M4/M7 (DSP), v8-M = M23/M33 (TrustZone), v8.1-M = M55/M85 (Helium).
ASIL: Automotive Safety Integrity Level. ISO 26262 classification A–D for the rigor of safety mechanisms required.
AUTOSAR: AUTomotive Open System ARchitecture. Layered software architecture standard used in automotive ECUs (Classic Platform on Cortex-R/Cortex-M, Adaptive on Cortex-A).
AXI: Advanced eXtensible Interface. ARM AMBA bus protocol for high-throughput SoC interconnect; used by Cortex-A and Cortex-M7.

B

3 terms

BASEPRI: Cortex-M register that masks all exceptions at or below a given priority. Used by RTOSes for fast critical sections (ARMv7-M+).
BLE: Bluetooth Low Energy. Short-range radio standard for low-power devices (smartwatches, IoT sensors).
BSRR: Bit Set/Reset Register. STM32 GPIO register for atomic single-cycle pin set or clear without read-modify-write.

C

4 terms

CAN / CAN-FD: Controller Area Network. Differential serial bus for vehicles and industrial machines. CAN-FD = Flexible Data-rate (up to 8 Mbps payload).
CFSR: Configurable Fault Status Register at 0xE000_ED28. Tells you why a HardFault, MemManage, BusFault, or UsageFault triggered.
CMSIS: Cortex Microcontroller Software Interface Standard. ARM-provided headers + intrinsics + driver model used by every vendor SDK.
CORDIC: Coordinate Rotation Digital Computer. Hardware accelerator for sin/cos/atan implemented as a peripheral on STM32G4 — much faster than soft-float trig.

D

3 terms

DMA: Direct Memory Access. Engine that moves data between memory and peripherals without CPU involvement.
DMIPS: Dhrystone MIPS — synthetic benchmark used to compare CPU performance per MHz across cores.
DSHOT: Digital protocol for talking to brushless ESCs. PWM-encoded 16-bit packets at 150/300/600/1200 kHz; replaces analogue PWM in drones.

E

3 terms

EKF: Extended Kalman Filter. Sensor fusion algorithm combining gyro + accel + GPS + baro into a position+attitude estimate.
EXC_RETURN: Magic 0xFFFFFFFx value loaded into LR on Cortex-M exception entry. Encodes which stack to unstack from and what mode to return to.
EXTI: STM32 External Interrupt controller. Routes GPIO edges (rising/falling) to the NVIC.

F

3 terms

FOC: Field-Oriented Control. Motor-control technique that controls the rotor field directly via Park/Clarke transforms; produces smoother torque than block commutation.
FPU: Floating-Point Unit. Hardware single-precision (Cortex-M4F) or single+double precision (M7/M33/M55/M85) IEEE-754 arithmetic.
FreeRTOS: The most-used embedded RTOS. MIT-licensed, ~6 KB minimum, ports to essentially every Cortex-M.

G

1 terms

GIC: Generic Interrupt Controller. Cortex-A interrupt controller (the equivalent of NVIC on Cortex-M).

H

2 terms

Helium / MVE: M-profile Vector Extension. SIMD ISA on Cortex-M55/M85 that reuses the FPU register file as 8×128-bit vectors. Tail-predicated.
HSM: Hardware Security Module. On-die crypto coprocessor used in automotive ECUs (EVITA spec) for key storage, AES, signed firmware updates.

I

3 terms

I²C: Two-wire bus (SCL + SDA) for slow peripherals. Open-drain with pull-ups; supports clock-stretching and multi-master.
IPSR: Interrupt Program Status Register. Holds the active exception number when in handler mode (0 in thread mode).
ITCM / DTCM: Tightly Coupled Memory. Single-cycle SRAM directly attached to Cortex-M7/R4+ cores, bypassing the cache. ITCM for code, DTCM for data.

L

2 terms

LDREX / STREX: Cortex-M3+ exclusive load/store pair. Foundation of all lock-free atomic operations.
Lockstep: Two CPU cores executing identical instructions in parallel; a comparator faults if outputs ever differ. Detects random hardware faults; used on Cortex-R for ASIL-D.

M

4 terms

Matter: IP-based smart-home standard (CSA). Runs over Wi-Fi, Thread, or Ethernet. Commissioning via BLE.
MMU: Memory Management Unit. Translates virtual to physical addresses; required for Linux and other rich OSes. Cortex-A only.
MPU: Memory Protection Unit. Region-based access control (R/W/X per region). Present on Cortex-M3+ and Cortex-R; simpler than MMU.
MSP / PSP: Main / Process Stack Pointer. Cortex-M has two banked SPs — MSP for handlers and pre-RTOS, PSP for user tasks under an RTOS.

N

1 terms

NVIC: Nested Vectored Interrupt Controller. Tightly-coupled to every Cortex-M core. Up to 240 IRQs, 256 priority levels (vendor-configurable).

O

1 terms

OCPP: Open Charge Point Protocol. JSON-over-WebSocket-TLS API every commercial EV charger speaks to its cloud management system.

P

5 terms

PACBTI: Pointer Authentication + Branch Target Identification. ARMv8.1-M security extensions — defeats ROP/JOP attacks.
PendSV: Pending Supervisor exception (#14). The trick RTOSes use to perform context switches *after* higher-priority ISRs return.
PrimaSK: Cortex-M mask register. Setting it to 1 disables all maskable exceptions (NMI + HardFault still fire).
PSCI: Power State Coordination Interface. The standardized way Linux talks to TF-A on ARMv8-A to power CPUs on/off and reboot.
PWM: Pulse-Width Modulation. Time-encoded analogue output via a digital pin. Used for motor drive, LED dimming, audio.

R

2 terms

RCD: Residual Current Device. Trips power if the live and neutral currents don't balance — required ground-fault protection in EV chargers.
RTOS: Real-Time Operating System. Tiny preemptive scheduler with deterministic timing.

S

9 terms

SAU / IDAU: Security Attribution Unit + Implementation-Defined Attribution Unit. ARMv8-M hardware that decides whether each memory access is Secure or Non-secure.
SBI: Supervisor Binary Interface — boot+runtime API for RISC-V. ARM's equivalent is PSCI.
SCB: System Control Block. Cortex-M peripheral at 0xE000_ED00 containing CPUID, CFSR, VTOR, AIRCR, and many fault/system registers.
SHC / SVC: Supervisor Call. SVC #imm triggers SVCall exception (#11) — RTOSes use it to enter privileged mode.
Shiki: Syntax highlighter used by this site. Generates pre-coloured spans at build time; no client-side highlighting cost.
SPI: Serial Peripheral Interface. 4-wire synchronous serial bus. Up to half PCLK in master mode (~40 MHz on STM32F4).
SRAM: Static RAM. Volatile fast memory used for stacks, heap, and DMA buffers in microcontrollers. Typically 16 KB – 1 MB.
STO: Safe Torque Off. IEC 61800-5-2 SIL-3 mandatory hardware input that disables motor-drive gate drivers regardless of firmware state.
SysTick: Universal 24-bit Cortex-M downcounter at 0xE000_E010. Standard RTOS tick source.

T

3 terms

Thread: 802.15.4 mesh networking. Low-power IP-over-radio, foundation of Matter for non-Wi-Fi devices.
TLB: Translation Lookaside Buffer. Cache of MMU virtual-to-physical translations on Cortex-A.
TrustZone: ARM's hardware partitioning. Cortex-M: per-access SAU+IDAU. Cortex-A: NS bit + EL3 secure monitor.

U

1 terms

UART: Universal Asynchronous Receiver/Transmitter. Two-wire (TX, RX) serial bus; the first peripheral you wire on a new board.

V

1 terms

VTOR: Vector Table Offset Register at 0xE000_ED08. Lets firmware relocate the vector table to RAM or a different flash region.

Z

1 terms

Zephyr: Linux Foundation embedded OS. Full stack with drivers, networking, BLE — bigger than FreeRTOS but provides much more out of the box.