Cortex-M architecture comparison

There are now nine commercially relevant Cortex-M cores, spanning three architecture profiles (ARMv6-M, ARMv7-M, ARMv8-M) and four generations of microarchitecture. Picking the right one for a new design is most of the work of picking an MCU — and it's harder than it sounds because vendors mix-and-match optional features. An M33 from STM might have FPU+DSP+TrustZone; an M33 from a low-cost competitor might have only the base feature set. This page is the single reference for what each core can do, not what any specific part does.

The table below covers the architectural envelope. For per-vendor option choices, you have to read the datasheet — there is no shortcut.

The master comparison table

Pipeline depth and IPC

Pipeline depth is a rough proxy for clock-frequency headroom — deeper pipelines mean smaller per-stage logic and faster clocks, at the cost of larger mispredict penalties.

Note the M85's deeper pipeline doesn't kill perf because of branch prediction — a correctly predicted branch is zero penalty. The M7, with weaker prediction, eats its 5–7 cycle penalty on every mispredicted branch.

ISA features

What instructions you actually have, by core:

Bit-banding (the M3/M4-only feature that aliases each bit of a register region to a word at a different address) is dead in v8-M. Don't write portable code that depends on it.

Memory and bus

Cache and TCM are big lever points. Cached cores get high mean throughput from flash but require DMA coherency management. TCM gets deterministic single-cycle latency without cache management — the right place for ISRs and DMA buffers.

Security: MPU, TrustZone, PAC/BTI

The M85 stands alone with PAC and BTI. For products that need certified control-flow integrity, this is currently the only Cortex-M option.

Floating-point

If you need double precision, your only choices are M7, M55, or M85. The M33 is single-precision only; double-precision FP on M33 goes through software helpers and is roughly 100× slower than single-precision native.

NVIC priorities and IRQ count

Most actual silicon ships with 3 or 4 priority bits regardless of architectural maximum. Vendors trim NVIC area aggressively.

DMIPS and CoreMark

Numbers are ARM-published reference benchmarks. Real silicon varies — memory latency, flash wait states, and cache hit rates all skew real-world results by 10–30%.

Choosing a core for a new design

A reasonable decision tree:

1. Need security partition (TrustZone-M)? → M23, M33, M55, or M85. Skip M0/M0+/M3/M4/M7.
2. Need ML inference at low power? → M55 + Ethos-U. M85 if no NPU is available.
3. Need maximum single-thread perf? → M85 (new design) or M7 (legacy / cheaper silicon today).
4. Need DSP/SIMD without ML? → M33+DSP, M55, or M85. M4 if cost dominates.
5. Need FPU? → M4, M7, M33+FPU, M55, or M85.
6. Just need a small low-power core? → M0+ first, M23 if security is required.

Treat M0, M3, and M4 as legacy for new designs — they're fine in established product families but offer nothing v8-M alternatives don't. M7 is the exception: still has the highest deployed install base for high-perf MCU work, and the SP/DP FPU is sometimes cheaper than M85.

Cross-references

• Cortex-M0 · M0+ · M3 · M4 · M7 · M23 · M33 · M55 · M85
• The Cortex-M lineup overview
• ARMv7-M vs ARMv8-M
• ISA families
• ARM TRMs for each core (DDI series)