Stack-frame visualizer.

Drop in the 8 words Cortex-M pushes on exception entry (R0, R1, R2, R3, R12, LR, PC, xPSR). Each is labelled with its meaning, xPSR is decoded into IPSR / NZCV / Thumb bit, and a missing Thumb bit on PC is flagged loudly.

Stacked words

FPU frame

SP at entry

+00

+04

+08

+12

+16

+20

+24

+28

Try a sample

+00

R0

SP + 0 → 0x20007FE0

General-purpose register R0 at exception entry (first arg / caller-saved).

—

+04

R1

SP + 4 → 0x20007FE4

General-purpose register R1 (second arg / caller-saved).

—

+08

R2

SP + 8 → 0x20007FE8

General-purpose register R2 (third arg / caller-saved).

—

+12

R3

SP + 12 → 0x20007FEC

General-purpose register R3 (fourth arg / caller-saved).

—

+16

R12

SP + 16 → 0x20007FF0

Intra-procedure scratch (IP). Caller-saved.

—

+20

LR

SP + 20 → 0x20007FF4

Link register at exception entry — the return address the interrupted code expected to return to.

—

+24

PC

SP + 24 → 0x20007FF8

Return address — the address of the next instruction to execute on return. Often the faulting instruction itself for precise faults.

—

+28

xPSR

SP + 28 → 0x20007FFC

Program Status Register — IPSR (exception #), APSR (flags), EPSR (Thumb / IT state).

—

About this frame

On exception entry, the Cortex-M hardware automatically stacks 8 words onto the current stack: R0–R3, R12, LR, PC, xPSR. If the FPU is active and FPCCR.ASPEN=1, it also stacks S0–S15 + FPSCR (toggle "FPU frame" to add). The handler runs with a fresh AAPCS frame on top of this, and EXC_RETURN encodes which stack to unstack from on return.