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Interrupt latency calculator.

Pick a core, clock, and where your stack / vector table live. Get a cycle-by-cycle breakdown of exception entry — stacking 8 words, FPU frame, vector fetch, pipeline refill — plus tail-chain and late-arrival numbers for back-to-back IRQs.

Core & memory

FPU

No FPU push on entry.
Worst-case entry latency
14cycles≈ 83.3 ns
Tail-chain
6 cyc
35.7 ns
Late-arrive
7 cyc
41.7 ns

Cycle breakdown

  1. 1.
    Detect & start
    NVIC recognises pending exception
    2 cyc
  2. 2.
    Stack R0–R3, R12, LR, PC, xPSR
    8 word push to cacheable SRAM
    8 cyc
  3. 3.
    Vector fetch
    read handler address from vector table (flash, 0WS)
    2 cyc
  4. 4.
    Pipeline refill at handler
    fetch first handler instruction
    2 cyc
  5. Total
    14 cyc
What this means
  • Entry: cycles between the IRQ asserting and the first instruction of the handler running.
  • Tail-chain: if another exception is pending when this one finishes, the CPU skips unstack/restack and jumps straight to the next handler.
  • Late-arrive: if a higher-priority exception arrives mid-stacking, the CPU switches to that handler without re-stacking.
  • FPU lazy stacking (FPCCR.LSPEN=1) is on by default in CMSIS. Disable it only when you need predictable timing on FPU-using handlers.